Label "testb1"
CopyInput 0
Push 3
CreateFrame 1

Label "testb1_0"
MatchRule
MatchAvailable
MatchVar 0
Consume 0
MatchedRule
MkInt 3
PushVar 0
CallPrim ">"
If "t_testb1_0_0"
MkInt 2
PushVar 0
CallPrim "<"
If "t_testb1_0_1"
MkInt 1
Goto "n_testb1_0_1"

Label "t_testb1_0_1"
MkInt 0

Label "n_testb1_0_1"
MkInt 1
PushVar 0
CallPrim "+"
MkTuple 2
Goto "n_testb1_0_0"

Label "t_testb1_0_0"
MkNone
MkNone
MkTuple 2

Label "n_testb1_0_0"
Unpack
CheckOutputs
Write 0
Write 1
Schedule

Label "testb2"
CopyInput 0
Push 3
CreateFrame 0

Label "testb2_0"
MatchRule
MatchAvailable
MatchInt 0
Consume 0
MatchedRule
MkInt 1
MkInt 1
MkTuple 2
Unpack
CheckOutputs
Write 0
Write 1
Schedule

Label "testb2_1"
MatchRule
MatchAvailable
MatchInt 1
Consume 0
MatchedRule
MkInt 0
MkInt 0
MkTuple 2
Unpack
CheckOutputs
Write 0
Write 1
Schedule

Label "or"
CopyInput 1
CopyInput 0
Push 3
CreateFrame 0

Label "or_0"
MatchRule
MatchAvailable
MatchInt 0
MatchAvailable
MatchInt 0
Consume 0
Consume 1
MatchedRule
MkInt 0
CheckOutputs
Write 0
Schedule

Label "or_1"
MatchRule
MatchAvailable
MatchAny
MatchAvailable
MatchAny
Consume 0
Consume 1
MatchedRule
MkInt 1
CheckOutputs
Write 0
Schedule

Box "testb1" "testb1" 20 10 1 2 1 "testb1_init" "testb1_handler" NullT
Rule "testb1" "testb1_0"
Require "testb1" True

Box "testb2" "testb2" 10 7 1 2 2 "testb2_init" "testb2_handler" NullT
Rule "testb2" "testb2_0" "testb2_1"
Require "testb2" True
Require "testb2" True

Box "or" "or" 6 7 2 1 2 "or_init" "or_handler" NullT
Rule "or" "or_0" "or_1"
Require "or" True True
Require "or" True True

Label "or_init"
Schedule

Label "testb1_init"
MkInt 0
Write 0
Schedule

Label "testb2_init"
MkInt 1
Write 0
Schedule
Stream "stdout" Out "s_write" "std_err" 2 1 0 NullT
Wire "stdout" 0 "stdout" 0 2 0 NullT

Label "s_read"
Input
Write 0
Schedule

Label "s_write"
CopyInput 0
Consume 0
Output
Schedule

Label "s_timeout"
MkTuple 0
Raise "Timeout"

Label "s_soverflow"
MkTuple 0
Raise "StackOverflow"

Label "s_hoverflow"
MkTuple 0
Raise "HeapOverflow"
Wire "testb1" 0 "testb1" 0 2 0 NullT
Wire "testb2" 0 "testb2" 0 2 0 NullT
Wire "or" 0 "testb1" 1 2 0 NullT
Wire "or" 1 "testb2" 1 2 0 NullT
Wire "stdout" 0 "or" 0 2 0 NullT